1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a structure of a bonding pad portion of a semiconductor device having a multilayer metal interconnection or metallization structure.
2. Disclosure of the Prior Art
Until now, in semiconductor devices which have multilayer metal interconnection structure of this type, mainly aluminum or aluminum alloy such as Al-Cu, Al-Si-Cu or the like has been used as the metal for interconnects. However, electromigration, stress migration and any other problems have occurred as interconnecting width and pitch get shorter and smaller. To solve these problems, gold or gold alloys have been used as the metal for interconnects.
Generally, a lift-off method, an etching method, a plating method due to resist-mask or the like has been considered to realize fine gold interconnects. Lately, the plating method due to resist-mask has been often used because of its dimensional accuracy and easy process.
A brief description of that method is as follows: First, a layer of titanium, platinum or the like is formed all over an insulating layer as an electron-supplying layer. Then, a photoresist is kept remained outside of interconnection patterns by the conventional photoresist process. Thereafter, the interconnection patterns are formed by a gold plating and then the photoresist is peeled off or removed. Finally, the electron-supplying layer which remains between the interconnection patterns is removed by etching whereas the interconnection patterns serve as a mask and are unremoved. There are a few etching methods. One is a chemical etching by a wet method. Another is a dry etching or an ion milling which make use of a reverse sputtering. The most appropriate method to make fine patterns among them is the dry etching using the reverse sputtering in the atmosphere of inactive gases which makes very few side etching.
However, there are some problems on this method. In the case that the surface of the lower layers is uneven, i.e. there are steep differences in level in the lower layers, some of the electron-supplying layer tends to remain unremoved even by etching and therefore it causes a short circuit, peeling-off or tearing-off and scattering in later processes, etc.
In order to avoid the formation of the uneven surface or steep differences in level in the lower layers, it is suggested that organic insulating layers which can be formed by coating, such as polyimides that include silicon (called silicon polyimide below), or inorganic insulating layers are to be used as interlayer insulating layers.
Referring now to FIG. 1, there is shown a sectional structure of a bonding pad portion for a wire bonding of the prior art semiconductor device, wherein interlayer insulating layers are used. On a semiconductor substrate 1, formed is a first metal interconnection layer which is not shown in the figure, on which a first interlayer insulating layer 3 is formed. A second metal interconnection layer which is not shown in the figure is formed thereon and furthermore a second interlayer insulating layer 7 is formed thereon. A layer formed by plasma CVD etc. is used as the first interlayer insulating layer 3 and an insulating layer which is coated and film-formed, such as silicon polyimide etc., is used as the second interlayer insulating layer 7. Then, hall 8 is made in the second interlayer insulating layer 7 and in the hall a third metal interconnection layer 11 is formed as a bonding pad.
Referring now to FIG. 2, there is shown a structure of an another prior art semiconductor device. On a semiconductor substrate 1, formed is a first metal interconnection layer which is not shown in the figure, on which a first interlayer insulating layer 3 is formed. A second metal interconnection layer 6 is formed thereon. An inorganic insulating layer formed by CVD, plasma CVD, etc. is used as the first interlayer insulating layer 3. Then, a second interlayer insulating layer 7 is formed thereon and hall 8 is made, which exposes a part of the second metal interconnection layer 6 mentioned above. An organic insulating layer, which is coated and film-formed, such as silicon polyimide, etc. is used as the second interlayer insulating layer 7.
Then, a third metal interconnection layer 11 is formed so that it covers the hall 8 made in the second interlayer insulating layer 7, which is comprised as a bonding pad.
In FIGS. 1 and 2, a field insulating layer and an electron supplying layer are omitted.
As mentioned above, a combination of the conventional insulating layer formed by coating and an interconnecting method, by which a gold layer or electron supplying layer is easy to remain at the place where the steep difference in level exists in the lower layer or at a deep vertical gap, causes the following problems. When cracking is tried to be avoided, there is a possibility of a short circuit by peeling-off of the gold or electron supplying layer remained at the deep vertical gap. On the other hand, when a short circuit by peeling-off is tried to be avoided, there is a possibility of cracking.
For example, in FIG. 1, the third metal interconnection film 11 is formed as a bonding pad in the hall 8 of the second interlayer insulating layer 7. In this case, even if mechanical pressure or impact on bonding is applied to the third metal interconnection layer 11, the pressure is not applied to the second interlayer insulating layer 7 and thus cracking in the second interlayer insulating layer 7 can be avoided. However, in this structure, the gold-plating layer or electron supplying layer which forms the third metal interconnection layer 11 tends to remain on the side 8a of the hall 8 on etching of the third metal interconnection layer 11. Thus, there is a possibility of a short circuit by its peeling-off in the subsequent processes.
On the other hand, in the structure as shown in FIG. 2, since the third metal interconnection layer 11 is so formed as to cover the hall 8, no etching is carried out at the side 8a of the hall 8 and no peeling-off at the side 8a takes place. However, there is a possibility of cracking in the second interlayer insulating layer 7 by the mechanical pressure on bonding and it will cause the reliability of the products to be lowered.
FIGS. 1 and 2 are examples of a three-layer interconnection (metallization) structure. Not only the three-layer structure but also a two-layer or multilayer (four and more) structure causes the same problem when the use of coated and film-formed insulating layers which are easy to crack by the mechanical pressure is combined with the interconnecting technique by which the gold layer or electron supplying layer is easy to remain at the above deep vertical gap in the lower layers.